USB PHY芯片 | 码农家园
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
Canovatech - CT25201_PHY
USB 2.0 PHY Verification
Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 2.0 Device Controller for SoC Designs | Cadence IP
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
Canovatech - CT20602
USB 2.0 Solutions | Arasan Chip Systems
DE10-Advance Hardware Manual revC Chapter5 USB OTG - Terasic Wiki
USB3300 USB HS Board USB high-speed PHY device for ULPI interface
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
Confidently Characterize Validate and Debug Your USB 31 Electrical PHY Designs | Tektronix
USB 2.0 PHY for SoC Designs | Cadence IP
USB 3.0 PHY for SoC Designs | Cadence IP
TUSB1210 data sheet, product information and support | TI.com
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
TUSB1210-Q1 data sheet, product information and support | TI.com
USB 2.0 Full High Speed Solution | NXP Semiconductors
ULPI - Kcchao
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
USB 2.0 PHY IP core | Arasan Chip Systems
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
HSIC USB 2.0 PHY IP
PCIe/USB/SATA PHY Appilcation example | Renesas
Mixed-Signal Verification for USB 2.0 Physical Layer IP
